A design automation methodology based on graph neural networks to model integrated circuits and mitigate hardware security threats

Suggested Citation

Mohammad Abdullah Al Faruque, Rozhin Yasaei and Shih-Yuan Yu (2024) “A design automation methodology based on graph neural networks to model integrated circuits and mitigate hardware security threats”. Available at: https://patents.google.com/patent/US20240338491A1/en (Accessed: August 21, 2025).